Muse Spark Open超快突破:单请求破千tokens/s

Muse Spark Open超快突破:单请求破千tokens/s

SGLang与ML基础设施正转向更大规模的GPU核——megakernel。本文从零用CUDA C++和PTX为Muse Spark Open构建megakernel,将Blackwell GPU单请求解码速度从517 tok/s提升至1109 tok/s。

Decode tokens per second, one request at a time: baseline 517, megakernel 1,109, 2.1 times as fast

Muse Spark Open采用传统MoE结构,每个token路由至256专家中的8个,专家权重以4位NVFP4存储,含62个解码层。

什么是megakernel?

普通GPU核仅执行单一操作,服务引擎需发射约1450个核完成一次解码步。若未充分优化,核间GPU会出现空闲。megakernel则让单一核常驻所有SM,同时运行多种任务,保持张量核、TMA、NVLink等引擎全速运转。

CPUs went from batch jobs to multiprogramming to operating systems; GPUs went from one kernel per operation to megakernels

模型与新张量并行

模型在8张GPU上以TP8划分。传统TP在两个MoE GEMM间仅一次all-reduce,而新方案在N维切分两个GEMM,引入fp4 all-gather与bf16 all-gather,虽多一步通信但总体通信量更低,扩展性更好。

One decoder layer in six steps, with five numbered stops where it waits for the other GPUs; the expert steps are marked as known only after the router runsThe expert GEMMs across eight GPUs: vanilla TP splits GEMM 1 on N and GEMM 2 on K and ends with one bf16 all-reduce; ours splits both on N, with an fp4 all-gather after GEMM 1 and a bf16 all-gather after GEMM 2

megakernel实现

每层仅发射一次核,覆盖从本层attention到下一层qkv投影与KV写入。每个核在144个SM上放置12个warp,不同warp分别负责KV加载、权重预取、张量核计算、SwiGLU及all-gather/reduce。

Four slots of a receive buffer: all empty before any store; two values landed and the reader keeps polling; all four landed and the reader goes

性能与投机解码

单步解码耗时从12.9 ms降至5.9 ms,核数量从1450减至97。配合DFlash V2 draft模型,每步验证16 token,平均接受6.6 token,达到1109 tok/s。

One decode step: baseline takes 12.9 ms (draft 1.16, verify 10.9) with 1,450 kernels; Megakernel takes 5.9 ms (draft 0.44, verify 5.3) with 97 kernels

megakernel内部优化

通过权重全缓存预取、指令缓存管理、多级同步(shared memory mbarrier、HBM flag、NVLink直接store)及无fence数据同步,实现近乎完美重叠。

Three places a prefetched weight can wait: straight into the shared-memory ring while the current op runs; into L2 for what does not fit, like the speculatively prefetched experts; or both, with the ring refilling from L2 instead of HBMTwo blocks of code run back to back: 20 KB + 100 KB fit in an SM's instruction cache of about 128 KB, and the 100 KB block runs at its solo 12.4 µs; 100 KB + 100 KB do not fit, and every pass takes 19.5 µsWhere threads meet to synchronize: two warps in the same SM wait on an mbarrier in shared memory; warps on two SMs of one GPU meet at a flag in HBM, polled; a warp on another GPU stores over NVLink straight into this GPU's HBM, where the reader polls for the dataFence-free data synchronization: with a weight stream in flight, the fence before the flag takes 3.6-4.0 µs; when the data is its own flag, the reader starts as soon as the data lands

展望

未来将支持更大批次,并向GPU操作系统方向演进。